The present embodiments relate to digital memory circuits, and are more particularly directed to dynamic logic memory addressing circuits, systems, and methods with reduced capacitively loaded predecoders.
The technology of many modern circuit applications continues to advance at a rapid pace, with consideration given to all aspects of design. Designers constantly strive to increase performance, while maximizing efficiency. One incredibly prolific type of circuit, and one which is highly developed, is digital memory. Digital memories are implemented either as stand-alone products, or as part of a larger circuit such as a microprocessor. With respect to performance of the digital memory, greater overall circuit speed is achieved by improving the speed of various circuits of the memory, where those circuits operate to receive an address, decode the address, and either input or output information at the storage location specified by the address. Consequently, in memory design the circuits which make up speed-limiting portions or affect the speed of the memory are constantly scrutinized and re-designed to increase the overall speed. Increased speed increases performance and, therefore, permits more detailed and sophisticated input/output capabilities in a shorter amount of time. As another consideration, the cost of the device also must be considered. This cost is often reflected in the overall size of the memory architecture as well as in connection with its power requirements. Thus, a desirable memory design balances the considerations of speed with cost, and is reviewed extensively by the present embodiments described below.